1. Field of the Invention
This invention relates to a programmable functional device, more specifically to switches used for the programmable functional device.
2. Description of the Related Art
A programmable logic device (hereinafter referred to as PLD) is known as large scale integrated circuit(hereinafter referred to as LSI) capable of programming logic functions by the user(s). The PLD has a wide variety of devices such as a programmable logical array (hereinafter referred to as PLA) and a field programmable gate array (hereinafter referred to as FPGA). The PLA is an example of a small scale PLD having a basic structure consisting of an AND portion and an OR portion. Also, the FPGA is an example of a large scale PLD.
These PLDs are constructed so as to provide a number of logic circuits and the like on the chip for the LSI, and the logic circuits are connected to one another through switches capable of programming. So that, it is possible to realize desired logic functions by switching the switches in accordance with the programs programmed by the user(s).
Thus, an LSI having desired logic functions can be realized in a short period of time by utilizing the PLD.
However, the PLD in the prior art described in the above has the following disadvantages. A fuse 2 shown in FIG. 9A is used as a switch capable of programming in the prior art. Disconnection of a line 4 and a line 6 can be done by burning out the fuse 2. However, it is not possible to connect the fuse 2 again, once the fuse 2 has been burned out. So that, the logic functions can not be rewritten as a result of disconnection.
To resolve the problem stated in the above, an electrically erasable and programmable read only memory (hereinafter referred to as EEPROM) 8 shown in FIG. 9B can be used as the switch instead of the fuse 2. Although rewriting of the logic functions can be achieved as a result of using the EEPROM 8, it requires a long time to rewrite the logic functions. Therefore, the EEPROM 8 cannot be applied to a switch that needs to be operated under real-time bases.
In order to realize simulated rewriting of the logic functions under real-time bases while using the EEPROM 8, a method using two individual units each of which includes a certain numbers of logic circuits etc. (hereinafter, each of the unit is referred to as a tile) is proposed. In this method, a total of two tiles being twice the number of tiles used in regular operation are mounted, and rewriting of the logic functions is carried out one after another exclusively. In other words, the rewriting of one tile is carried out while the other tile is performing routine data processing as regularly executed by a PLD. Although the method allows the EEPROM 8 to prevent suspension of processing for long period of time when the rewriting is carried out, the area of the chip must be increased to twice as much for mounting the two tiles.
A static random access memory (hereinafter referred to as SRAM) 10 shown in FIG. 9C can be used in order to carry out rewriting of the logic functions under real-time bases. Although rewriting of the logic functions under real-time bases can be carried out by utilizing the SRAM 10, another non-volatile memory device is required to secure the contents of the rewriting because the SRAM is a volatile memory device.